3 bit flash adc thesis report pdf
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Tables And Figures In Thesis Proposal
Refworks Account Login. Open Collections. UBC Theses and Dissertations. Featured Collection. While multi-channel ADCs can achieve high speeds, they often require extensive and costly post-fabrication calibration. A single-channel 4-bit flash ADC, suitable for abovementioned or similar applications, implemented entirely using current-mode logic CML blocks, is presented. CML implementation allows for high sampling rates, while typically providing low power consumption at high speeds.
To improve the conversion rate, both the analog comparator array and the digital encoder parts of the ADC are fully pipelined. Furthermore, the logic functions in the encoder are reformulated to reduce wire crossings and delay and to equalize the wires lengths in the layout.
To keep the design simple, inductors are avoided. As a result, a compact design with small wire parasitics is achieved. Moreover, some geometric layout techniques, including a common-centroid layout for the resistor ladder, are introduced to reduce the effect of mismatches to eliminate the use of digital calibration. The ADC is designed and fabricated in 0. It achieves an effective number of bits ENOB of 3. The ADC consumes 43mW from a 1. It also reports the best power performance among the 4-bit ADCs with similar or higher speeds.
The active area is also among the smallest reported. The related formulas in the literature are not accurate for low-resolution ADCs, and yet they do not take the input waveform into account.
Two standard waveforms, ramp and sinusoid, are considered here. The SNR formulas are derived and confirmed by simulation results. Highlighted comparators are selected during calibration [33][39]. In simulations, randomly generated offset voltages with zero mean and standard deviation of 1 LSB are applied to the comparators.
Horizontal axes are the comparator numbers. In figures a to c , dummy comparators are shown in gray color. The encoder with no-pipelining is used as the base circuit for this comparison The top waveform is related to the correct switching time. The bottom waveforms are related to earlier or later switching. The respective codes are shown below the waveforms.
It is assumed that all other bits are switching at the right time.. The delay for node M is estimated as RCm 2 2 It was an honor to work with them, and I thank them deeply for giving me the opportunity to join their research groups.
I am thankful to my colleague Ph. Also, I would like to acknowledge Dr. Roberto Rosales for his technical assistance and willingness to help. I wish to express my deepest appreciation to my parents and brothers and sisters for their unconditional love and endless support. They have always been the greatest source of inspiration for me, and I dedicate this thesis to them. A majority of these applications require 4 to 6 bits of resolution at mutli-GHz conversion rates.
For high-speed low-to-medium resolution, ADCs the most appropriate architecture is flash. This architecture is widely used in ADCs with resolutions of 7 bits or less.
For 4-bit resolution, multi-GHz rates are also achieved using time-interleaved architectures. It is important that such ADCs be implemented in a standard CMOS process for easy integration with other digital signal processing circuits. The main challenges in designing high-speed CMOS flash ADCs are optimizing the speed and power, static and dynamic offset reduction, calibration, and low supply voltage operation [9].
One application of high-speed low-to-medium resolution ADCs is in serial links. Because of their lower cost and lower power consumption, serial links are atracting more and more attention in wireline data transmission. The conventional binary pulse amplitude modulation 2-PAM cannot accommodate the high-speed data rates of many modern 2 applications due to the intrinsic bandwidth limitation of the transmission medium.
To address this problem, multi-bit-per-symbol modulations multi-level PAM appear as an attractive solution [12].
As an example, for a given transfer rate, an 8-PAM modulation scheme reduces the symbol rate of the channel to one third of a conventional 2-PAM modulation. As a result, the inter-symbol interference ISI in the channel is also reduced. Figure 1. The serial link data rate is the same as the parallel data rate. In the case of an 8-PAM data transmission, the waveforms are shown in Figure 1. For the proper operation of the receiver, the analog signal should be sampled close to the center of each symbol.
Alternatively, the received data can be oversampled, as shown in Figure 1. The design is targeted for applications such as high-speed serial links and UWB that require 4 bits of resolution at multi-GHz speeds. However, the applicability of the techniques to higher resolution flash ADCs such as 5- and 6-bit ADCs are also considered. The ADC is targeted for 0. However, the circuit should be portable to smaller feature size CMOS technologies with lower supply voltages. All the ADC sub-blocks including the comparators and the encoder are implemented using current-mode logic CML circuits.
The similarity of the sub-blocks facilitates increased matching in the layout. Differential operation results in higher immunity to the common-mode noise, while low-swing operation leads to lower noise generation. This low-swing operation is important, especially at high speeds. In addition to the CML implementation, the comparator array and the encoder are fully pipelined.
Also, as the inductors are not used, the ADC has one of the smallest reported active areas in those technologies. A Gray coding encoder is used to increase the immunity against bubble errors and metastability. As a result, complex digital schemes such as Wallace tree counting [18] or digital averaging [19] are avoided. Part of this power saving is also due to the CML implementation, in which the power consumption of each block is dictated by a bias current. Therefore, the power does not increase with higher sampling rates.
An important challenge in the encoder layout is the connection of the comparator outputs to the encoder inputs. Long routings and different wiring lengths for different comparator outputs and crossings of the wires adversely affect the encoder speed.
In this work, the expressions for converting the thermometer codes to Gray codes are reformulated in order to overcome these layout issues. The proposed reformulation [17] takes advantage of the special properties of thermometer codes. In the new formulas, only the outputs of the physically adjacent comparators in the layout are connected to the same 6 gate in the encoder.
Therefore, all long wires that connect the comparator outputs to the first gate level in the encoder are replaced with short wires of equal length. As a result, the total number of long wires and wiring crossovers are greatly reduced. Both these solutions would result in higher complexity and also higher power consumption. Therefore, resistors in the ladder are prone to systematic mismatches arising from fabrication process variations, and can potentially increase the decision-level offsets DLOs — refer to Appendix B of the ADC.
A common-centroid layout is introduced in this work for the resistor ladder to reduce the effect of those mismatches [17]. Each resistor is first broken into a number of parallel segments such that the resistor ladder forms a grid of resistors. The resistor grid is then twisted to interleave the resistor segments symmetrically such that the structure ends up possessing a common center.
This technique is more effective in flash ADCs with a larger area e. Moreover, it can be used in flash ADCs with higher resolutions, as they require a larger on-chip area for the resistor ladder, and are also more sensitive to the offsets of the reference voltages.
In addition, other formulas are generic and do not take the input waveform into account. In this thesis, accurate SNR formulas are derived versus the INL performance for two different input waveforms: a ramp signal, as a good representative of a uniformly distributed input waveform; and a sinusoidal signal.
Chapter 3 covers the design details of the proposed 4-bit flash ADC including the block diagram, architecture and circuit design of the comparator and the encoder, pipelining and CML implementation, and reformulation in the encoder for speed improvement.
Chapter 4 presents the layout techniques used in the design, the test setup and the measurement results for the flash ADC. Pipeline ADCs [23] are usually used for high resolutions. However, large latency is a drawback, and also proper sampling at higher rates is challenging. Folding ADCs [24] consume less power and have lower latency as well as the possibility of operation at higher sampling rates. However, they suffer from the limited bandwidth of the analog path. Flash [2][5][8][9][21][25]—[29] is the architecture of choice for a high-speed ADC design, for applications that require 6 bits of resolution or lower.
Interpolation is also an option in a flash ADC [26] that reduces the power consumption by removing some preamplifiers in the preamplifier array. However, as each preamplifier drives more than one comparator, it comes at the cost of reduction in the speed, as the capacitance load for each preamplifier increases.
Multi-channel architectures, such as frequency- or time-interleaved systems, are alternative options in achieving very high-speed circuits. However, these parallel ADCs require extra circuit area and usually suffer from mismatches among the channels that call for costly calibration algorithms [6]—[8]. The input signal of the ADC is compared against evenly-spaced reference voltages generated by a resistor ladder. Comparators, including several amplification-and-latching stages, amplify the differences between the input signal and those reference voltages.
They deliver the comparison results as an array of digital bits or a codeword to the encoder. The encoder converts the thermometer code to a Gray or a binary code. Flash ADCs have a simple architecture.
ECE , Analog Integrated Circuit Design, High Speed Flash ADCs, Dec 1. Abstract— In this report we will discuss different issues in this ADC. Using two converters with three bit resolution, the output would have 6 bit resolution. A thesis report submitted in partial which is utilized to simulate the three blocks of flash ADC An Efficient Design of 3bit and 4bit Flash ADC A.
Summarize in your own words what the single main idea of the essay is. Paraphrase important supporting points that come up in the essay. Consider any words, phrases, or brief passages that you believe should be quoted directly.
